The present invention relates to a semiconductor memory circuit device comprised of a plurality of memory-cell arrays, each memory-cell array comprises a plurality of integrated injection logic elements.
At present, integrated injection logic elements (hereinafter referred to as IILs), are suitable elements for fabricating a memory circuit device because such IILs can be formed, as memory cells, with very high integration density. Such an IIL memory cell has been disclosed in, for example "Superintegrated memory shares functions on diffused islands", Electronics, Feb. 14, 1972, Pages 83 through 85, which mentions the basic idea of the IIL element.
Thus, the IILs can contribute to realize a superintegrated memory circuit device. However, on the other hand, the IILs have a defect in that it is difficult to perform very high speed read and write operations in the IIL memory circuit device due to the presence of a parasitic capacitor and a parasitic resistor, both of which are formed in the bulk for fabricating the IIL memory cells.
Therefore, it is an object of the present invention to provide a semiconductor memory circuit device, comprised of the IIL memory cells, which has a capability for performing very high speed read and write operations.